Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK

Title from PDF of title page viewed January 14, 2020Thesis advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 54-56)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City. 2019As the technology node scales down, the coupling capacitance between the adjacent metal lines increases. With an increase in this electrostatic coupling, the unwanted signal interference also increases, which is popularly called as Crosstalk. In conventional circuits, the Crosstalk affects either functionality or performance or both. Therefore the Crosstalk is always considered as detrimental to the circuits, and we always try to filter out the Crosstalk noise from signals. Crosstalk Computing Technology tries to astutely turn this unwanted coupling capacitance into computing principle for digital logic gates[1, 2]. The special feature of the crosstalk circuits is its inherent circuit mechanism to build polymorphic logic gates[3]. Our team has previously demonstrated various fundamental polymorphic logic circuits [1-6,16-18]. This thesis shows the design of the large-scale polymorphic crosstalk circuits such as Multiplier–Sorter, Multiplier–Sorter–Adder using the fundamental polymorphic gates, and also analyzes the Power, Performance, and Area (PPA) for these large-scale designs. Similar to the basic and complex polymorphic gates, the functionality of the large-scale polymorphic circuits can also be altered using the control signals. Owing to their multi-functional embodiment in a single circuit, polymorphic circuits find a myriad of useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. [3]. Also, in this thesis, a lot of studies have been done on the variability (PVT analysis) of Crosstalk Circuits. This PVT variation analysis establishes the circuit design requirements in terms of coupling capacitances and fan-in limitation that allows reliable operation of the Crosstalk gates under Process, Voltage and Temperature variations. As an example, I also elaborate on the reason for which the full adder can’t be implemented as a single gate in the crosstalk circuit-style at lower technology nodes. Though we designed a variety of basic and complex logic gates and crosstalk polymorphic gates, the biggest question is “Will these crosstalk gates work reliably on silicon owing to their new circuit requirements and technological challenges?”. Trying to answer the above question, the whole thesis is mainly focused on the physical implementation of the crosstalk gates at 65nm. I will detail the steps that we have performed while designing the crosstalk circuits and their layouts, the challenges we faced while implementing the new circuit techniques using conventional design approaches and PDK, and their solutions, specifically during layout design and verification. The other potential application of crosstalk circuits is in non-linear analog circuits: Analog-to-Digital Converter (ADC) [4], Digital-to-Analog Converter (DAC), and Comparator. In this thesis, I have shown how the deterministic charge summation principle that is used in digital crosstalk gates can also be used to implement the non-linear analog circuits.Introduction -- Polymorphic Crosstalk circuit design -- Practical realization of Crosstalk circuits -- PVT variation analysis -- Difficulties or errors in layout design and full chip details -- Potential miscellaneous applications -- Conclusion and future wor

A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs

Crosstalk computing, involving engineered interference between nanoscale metal lines, offers a fresh perspective to scaling through co-existence with CMOS. Through capacitive manipulations and innovative circuit style, not only primitive gates can be implemented, but custom logic cells such as an Adder, Subtractor can be implemented with huge gains. Our simulations show over 5x density and 2x power benefits over CMOS custom designs at 16nm [1]. This paper introduces the Crosstalk circuit style and a key method for large-scale circuit synthesis utilizing existing EDA tool flow. We propose to manipulate the CMOS synthesis flow by adding two extra steps: conversion of the gate-level netlist to Crosstalk implementation friendly netlist through logic simplification and Crosstalk gate mapping, and the inclusion of custom cell libraries for automated placement and layout. Our logic simplification approach first converts Cadence generated structured netlist to Boolean expressions and then uses the majority synthesis tool to obtain majority functions, which is further used to simplify functions for Crosstalk friendly implementations. We compare our approach of logic simplification to that of CMOS and majority logic-based approaches. Crosstalk circuits share some similarities to majority synthesis that are typically applied to Quantum Cellular Automata technology. However, our investigation shows that by closely following Crosstalk's core circuit styles, most benefits can be achieved. In the best case, our approach shows 36% density improvements over majority synthesis for MCNC benchmark